1. Field of the Invention
The present invention relates generally to digital circuits for providing delay of digital signals, and more particularly to a high resolution digital programmable delay circuit.
2. Description of Background
Modern digital logic circuits, such as those used in digital data processors, are characterized by short signal propagation times which are enhanced by decreased switching element (e.g. transistor) sizes and increased integration density. The short signal propagation times are exploited by reducing clock cycle times so that logic functions and data processing can be carried out more rapidly.
However, signal propagation time is necessarily finite and non-uniform due to capacitances and resistances of inter-connections and other loads such as those presented by the gates of CMOS devices which are currently the logic circuit technology of choice for most digital circuits and the signal propagation time within the circuits, themselves. The non-uniformity of signal propagation time has increased with digital processor complexity and burdensome design analyses are generally required to determine critical signal paths and maintain propagation time within tolerances in those critical paths. Even non-critical paths may present problems and cause errors of logic function in relatively simple circuit configurations and which cannot be reliably predicted.
Consider, for example, a circuit in which two related signals are propagated in parallel such as respective bits of a single byte of binary code representing a character or number.
If a logical combination of those two signals or bits is to be done, it is clearly imperative that either signals or bits be present and determinable as being of the appropriate logic state when the logic function is allowed to occur in order to avoid errors. Of course, it would be possible to latch signals at each point of the propagation path or to delay the logical operation until all signals are unconditionally settled to a stable logic state.
However, either such possibility would greatly reduce the operational speed of the overall logic circuit or processor. Thorough design analysis and adjustment of propagation time of each node of each signal propagation path would be economically prohibitive and does not guarantee the performance of the circuit. Accordingly, it is common practice to provide programmable delay elements in such signal paths to delay selected ones of related signals to correspond to the last to arrive in order to automatically synchronize their arrival at a particular node.
In general, it is also common practice to generate delays in digital signals by propagating signals through a plurality of rapidly switched identical stages such as serial pairs of inverter circuits and which are arrayed such that propagation time over connections between stages is substantially constant. While some variation in propagation time is inevitable, the propagation time through a pair of inverters is a sufficiently small time increment to approximate the required delay with a resolution which is short compared to clock cycle time. However, since propagation time may vary between stages and collectively over a plurality of stage (e.g. due to temperature, supply voltage and other operational and environment conditions, it is generally necessary to provide for empirical determination of the number of stages which will provide a required delay period at any given time in order to suitably program a delay element.
The ability to program such delay elements potentially reduces the design burden of designing particular delay elements for each node of a circuit path. However, it should be appreciated that delay elements can consume significant amounts of chip space, depending on the maximum amount of delay to be accommodated. While the maximum delay can be estimated, the maximum delay must be matched fairly closely with the actual delay in order to avoid excessive consumption of chip space and specific designs of delay elements for specific maximum delays may be required, depending on other operational constraints such as so-called set-up time.
That is, if delays are reasonably stable, it may be acceptable from a circuit design point of view to more-or-less permanently program the delay element with a few bits of read only memory or to use some type of propagation time monitoring and data collection circuit (external to the delay element) which adjustably reprograms the delay element bases on some statistical criteria in regard to error rate, propagation time variation, external conditions such as supply voltage or temperature of the like. This type of expedient allows the delay element to be physically formed on a chip in a step-and-repeat fashion since the delay stages may be made identically and the programming arrangement merely gates the output of each stage appropriately to derive the output from the stage which will provide the needed delay, such as by providing a simple multiplexer at each stage of the delay element.
On the other hand, there are many applications in which operation time is sufficiently critical that reprogramming is desirable upon the detection of any error and must be completed based on a single measurement or detection of actual propagation time, such as by sending a single signal transition through the delay element. Circuit designs capable of such short set-up time are substantially more complex since they must internally measure signal propagation time through the delay element and immediately adjust the location at which at which the output is to be taken. It is also necessary to provide equal delay from each tap of the delay line to the output of the multiplexer including the connections from the delay elements to the multiplexer inputs and accommodation of this requirement increases the complexity of the delay element design and requires unique layouts for delay elements of each different maximum delay to be produced.
To do this, it has been considered necessary to store propagation time information in the delay element and to use a single multiplexer having a number of inputs equal to the number of delay stages which is responsive to the stored propagation time data. This latter requirement prevents the delay element to be physically produced by the simple step-and-repeat fashion alluded to above since a different multiplexer design must be provided for each maximum delay. Again, there is a trade-off between chip space and the number of multiplexer designs which may be required in the overall logic circuit or processor design.
In summary, fast set-up time and ease of extendibility of the delay element architecture have been mutually exclusive. This mutual exclusivity can be readily understood from the fact that provision of a simple multiplexer at each stage of the delay element requires serial propagation of signals through a number of the multiplexers. Thus the propagation time through the serial chain of multiplexers after the signal has been tapped from one of the serially connected delay stages precludes the propagation time through the serially connected multiplexers from being directly measured consistent with propagation time data being stored in a latch in a replicable delay element stage. Therefore, a search for the correct stage at which to tap a signal from the delay line requires a number of repetitions to achieve the correct total delay through both a serial array of delay elements and a serial array of multiplexers. Viewed in a slightly different way, the circuit designer would prefer to avoid such problems and obtain a delay element circuit design and layout that would achieve the required delay.